203 search results - page 37 / 41 » Temporal Logic Verification Using Simulation |
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
1 In this paper, we propose a hybrid approach for estimating the switching activities of the internal nodes in logic circuits. The new approach combines the advantages of the simul...
103
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DAC
2009
ACM
16 years 20 days ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
198
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POPL
2003
ACM
15 years 12 months ago
2003
ACM
There is significant room for improving users' experiences with model checking tools. An error trace produced by a model checker can be lengthy and is indicative of a symptom...
105
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EMSOFT
2006
Springer
15 years 3 months ago
2006
Springer
Upper bounds on worst-case execution times, which are commonly called WCET, are a prerequisite for validating the temporal correctness of tasks in a real-time system. Due to the e...