203 search results - page 14 / 41 » Test Pattern Generator for Delay Faults |
116
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VTS
1996
IEEE
15 years 6 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
103
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DDECS
2007
IEEE
15 years 8 months ago
2007
IEEE
- As shown by previous studies, shorts between the interconnect wires should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools for targeti...
107
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VLSID
1996
IEEE
15 years 6 months ago
1996
IEEE
W epropose a coverage metric and a two-pass test generation method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and ...
122
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ET
2002
15 years 1 months ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
109
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VLSID
2002
IEEE
16 years 2 months ago
2002
IEEE
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...