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VTS
2002
IEEE
138views Hardware» more  VTS 2002»
13 years 11 months ago
Test Power Reduction through Minimization of Scan Chain Transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailog...
ICCAD
2007
IEEE
135views Hardware» more  ICCAD 2007»
14 years 3 months ago
A selective pattern-compression scheme for power and test-data reduction
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
Chia-Yi Lin, Hung-Ming Chen
VLSID
2005
IEEE
131views VLSI» more  VLSID 2005»
14 years 6 months ago
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Sh...
ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
13 years 11 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen