Sciweavers

2155 search results - page 124 / 431
» The EM-X Parallel Computer: Architecture and Basic Performan...
Sort
View
HPCA
1999
IEEE
15 years 9 months ago
Limits to the Performance of Software Shared Memory: A Layered Approach
Much research has been done in fast communication on clusters and in protocols for supporting software shared memory across them. However, the end performance of applications that...
Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jasw...
WSC
2008
15 years 7 months ago
High performance spreadsheet simulation on a desktop grid
We present a proof-of-concept prototype for high performance spreadsheet simulation called S3. Our goal is to provide a user-friendly, yet computationally powerful simulation envi...
Juta Pichitlamken, Supasit Kajkamhaeng, Putchong U...
IPPS
2007
IEEE
15 years 11 months ago
Exploring a Multithreaded Methodology to Implement a Network Communication Protocol on the Cyclops-64 Multithreaded Architecture
The IBM Cyclops-64 (C64) chip employs a multithreaded architecture that integrates a large number of hardware thread units on a single chip. A cellular supercomputer is being deve...
Ge Gan, Ziang Hu, Juan del Cuvillo, Guang R. Gao
EUROPAR
1999
Springer
15 years 9 months ago
Consequences of Modern Hardware Design for Numerical Simulations and Their Realization in FEAST
This paper deals with the influence of hardware aspects of modern computer architectures to the design of software for numerical simulations. We present performance tests for vari...
Christian Becker, Susanne Kilian, Stefan Turek
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
15 years 6 months ago
Fault tolerant nanoelectronic processor architectures
In this paper we propose a fault-tolerant processor architecture and an associated fault-tolerant computation model capable of fault tolerance in the nanoelectronic environment th...
Wenjing Rao, Alex Orailoglu, Ramesh Karri