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» The Entropy of FPGA Reconfiguration
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SIGARCH
2010
89views more  SIGARCH 2010»
14 years 8 months ago
Efficient reconfigurable design for pricing asian options
Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the in...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 7 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
15 years 5 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
DAC
2006
ACM
16 years 2 months ago
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
Wei Zhang, Niraj K. Jha, Li Shang
DATE
2009
IEEE
119views Hardware» more  DATE 2009»
15 years 8 months ago
Bitstream relocation with local clock domains for partially reconfigurable FPGAs
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
Adam Flynn, Ann Gordon-Ross, Alan D. George