Sciweavers

862 search results - page 117 / 173
» The amorphous FPGA architecture
Sort
View
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
15 years 6 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
IPPS
2007
IEEE
15 years 4 months ago
Reconfigurable Architecture for Biological Sequence Comparison in Reduced Memory Space
DNA sequence alignment is a very important problem in bioinformatics. The algorithm proposed by Smith-Waterman (SW) is an exact method that obtains optimal local alignments in qua...
Azzedine Boukerche, Jan Mendonca Correa, Alba Cris...
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
15 years 3 months ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 3 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
HOTI
2002
IEEE
15 years 2 months ago
Architecture and Hardware for Scheduling Gigabit Packet Streams
We present an architecture and hardware for scheduling gigabit packet streams in server clusters that combines a Network Processor datapath and an FPGA for use in server NICs and ...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...