862 search results - page 66 / 173 » The amorphous FPGA architecture |
DAC
1996
ACM
15 years 2 months ago
1996
ACM
In this paper, we study the problem of decomposing gates in fanin-unbounded or K-bounded networks such that the K-input LUT mapping solutions computed by a depthoptimal mapper hav...
JRTIP
2008
14 years 9 months ago
2008
Abstract Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficie...
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
15 years 10 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
APCCAS
2006
IEEE
14 years 11 months ago
2006
IEEE
Abstract-- Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory pl...
FPGA
2005
ACM
15 years 3 months ago
2005
ACM
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be p...