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CLEIEJ
2010
14 years 7 months ago
High Throughput and Low Cost Architecture for the Forward Quantization of the H.264/AVC Video Compression Standard
This work presents a dedicated hardware design for the Forward Quantization Module (Q module) of the H.264/AVC Video Coding Standard, using optimized multipliers. The goal of this...
Felipe Sampaio, Daniel Palomino, Robson Dornelles,...
ANCS
2008
ACM
14 years 12 months ago
Implementing an OpenFlow switch on the NetFPGA platform
We describe the implementation of an OpenFlow Switch on the NetFPGA platform. OpenFlow is a way to deploy experimental or new protocols in networks that carry production traffic. ...
Jad Naous, David Erickson, G. Adam Covington, Guid...
DSD
2008
IEEE
79views Hardware» more  DSD 2008»
15 years 4 months ago
Digital Systems Architectures Based on On-line Checkers
In this paper, a methodology for generating VHDL descriptions of hardware checkers is presented. It is shown how the methodology can be used to generate on-line checkers of commun...
Martin Straka, Zdenek Kotásek, Jan Winter
ISCAS
2006
IEEE
76views Hardware» more  ISCAS 2006»
15 years 3 months ago
Flexible hardware architectures for curve-based cryptography
— This paper compares implementations of elliptic and hyperelliptic curve cryptography (ECC and HECC) on an FPGA platform. We use the same low-level blocks to implement the basic...
Lejla Batina, Nele Mentens, Bart Preneel, Ingrid V...
FPGA
2007
ACM
163views FPGA» more  FPGA 2007»
15 years 4 months ago
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs
Boolean matching (BM) is a widely used technique in FPGA resynthesis and architecture evaluation. In this paper we present several improvements to the recently proposed SAT-based ...
Jason Cong, Kirill Minkovich