821 search results - page 5 / 165 » Time Dependent Processing in a Parallel Pipeline Architectur... |
IPPS
1999
IEEE
13 years 10 months ago
1999
IEEE
Abstract. This paper proposes a method for implementing fractal image compression on dynamically reconfigurable architecture. In the encoding of this compression, metric computatio...
IPPS
2007
IEEE
14 years 16 days ago
2007
IEEE
The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially...
IPPS
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
ISCA
2002
IEEE
13 years 11 months ago
2002
IEEE
An instruction set architecture (ISA) suitable for future microprocessor design constraints is proposed. The ISA has hierarchical register files with a small number of accumulator...
CF
2008
ACM
13 years 8 months ago
2008
ACM
To meet growing terabit link rates, highly parallel and scalable architectures are needed for IP lookup engines in next generation routers. This paper proposes an SRAM-based multi...