1640 search results - page 175 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
157
Voted
AES
2004
Springer
15 years 8 months ago
2004
Springer
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
134
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DSD
2006
IEEE
15 years 7 months ago
2006
IEEE
We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis m...
129
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VTC
2007
IEEE
15 years 9 months ago
2007
IEEE
—The Overbot is one of the original DARPA Grand Challenge vehicles now being used as a platform for autonomous vehicle research. The vehicle, equipped with a complete actuator an...
127
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DAC
2006
ACM
16 years 4 months ago
2006
ACM
In this paper, a Triangularization Based Structure preserving (TBS) model order reduction is proposed to verify power integrity of on-chip structured power grid. The power grid is...
120
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ASPDAC
2005
ACM
15 years 5 months ago
2005
ACM
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...