1640 search results - page 84 / 328 » Transistor-Level Timing Analysis Using Embedded Simulation |
138
Voted
DATE
2005
IEEE
15 years 8 months ago
2005
IEEE
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
127
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ECRTS
2005
IEEE
15 years 8 months ago
2005
IEEE
Slowdown based on dynamic voltage scaling (DVS) provides the ability to perform an energy-delay tradeoff in the system. Non-preemptive scheduling becomes an integral part of syste...
143
Voted
CGO
2004
IEEE
15 years 6 months ago
2004
IEEE
To meet the high demand for powerful embedded processors, VLIW architectures are increasingly complex (e.g., multiple clusters), and moreover, they now run increasingly sophistica...
94
Voted
DATE
2006
IEEE
15 years 8 months ago
2006
IEEE
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-onchips (SOCs). To increase the utilization of memory redundancy, the BISR t...
130
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ICCV
2009
IEEE
16 years 7 months ago
2009
IEEE
We use concepts from chaos theory in order to model
nonlinear dynamical systems that exhibit deterministic behavior.
Observed time series from such a system can be embedded
into...