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DFT
2006
IEEE
74views VLSI» more  DFT 2006»
15 years 5 months ago
Recovery Mechanisms for Dual Core Architectures
Dual core architectures are commonly used to establish fault tolerance on the node level. Since comparison is usually performed for the outputs only, no precise diagnostic informa...
Christian El Salloum, Andreas Steininger, Peter Tu...
EGH
2005
Springer
15 years 4 months ago
Optimal automatic multi-pass shader partitioning by dynamic programming
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
Alan Heirich
ASPLOS
2004
ACM
15 years 4 months ago
Deconstructing storage arrays
We introduce Shear, a user-level software tool that characterizes RAID storage arrays. Shear employs a set of controlled algorithms combined with statistical techniques to automat...
Timothy E. Denehy, John Bent, Florentina I. Popovi...
PADS
2003
ACM
15 years 4 months ago
Hybrid Packet/Fluid Flow Network Simulation
Packet-level discrete-event network simulators use an event to model the movement of each packet in the network. This results in accurate models, but requires that many events are...
Cameron Kiddle, Rob Simmonds, Carey L. Williamson,...
PADS
2003
ACM
15 years 4 months ago
Scalable RTI-Based Parallel Simulation of Networks
Federated simulation interfaces such as the High Level Architecture (HLA) were designed for interoperability, and as such are not traditionally associated with highperformance com...
Kalyan S. Perumalla, Alfred Park, Richard M. Fujim...