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121
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ISCAS
2003
IEEE
118views Hardware» more  ISCAS 2003»
15 years 8 months ago
SoC design integration by using automatic interconnection rectification
the interconnection among the IP cores with all description levels This paper presents an automatic interconnection rectification (AIR)technique to correct the misplaced interconne...
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
125
Voted
CHI
2008
ACM
16 years 3 months ago
WallCology: designing interaction affordances for learner engagement in authentic science inquiry
The broadening array of technologies available to support the design of classroom activity has the potential to reshape science learning in schools. This paper presents a ubiquito...
Brenda López Silva, Brian Uphoff, Darshan B...
119
Voted
CHI
2005
ACM
16 years 3 months ago
Roomquake: embedding dynamic phenomena within the physical space of an elementary school classroom
Authentic practice in science requires access to phenomena. In this paper, we introduce RoomQuake, an application designed to foster the growth of a community of learning around s...
Tom Moher, Syeda Hussain, Tim Halter, Debi Kilb
155
Voted
SIES
2009
IEEE
15 years 10 months ago
A flexible design flow for software IP binding in commodity FPGA
— Software intellectual property (SWIP) is a critical component of increasingly complex FPGA based system on chip (SOC) designs. As a result, developers want to ensure that their...
Michael Gora, Abhranil Maiti, Patrick Schaumont
208
Voted
TII
2011
206views Education» more  TII 2011»
14 years 10 months ago
Timing-Failure Risk Assessment of UML Design Using Time Petri Net Bound Techniques
Abstract—Software systems that do not meet their timing constraints can cause risks. In this work, we propose a comprehensive method for assessing the risk of timing failure by e...
Simona Bernardi, Javier Campos, José Merseg...