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HPCA
2008
IEEE
16 years 6 months ago
An OS-based alternative to full hardware coherence on tiled CMPs
The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
Christian Fensch, Marcelo Cintra
SC
2009
ACM
16 years 25 days ago
A case for integrated processor-cache partitioning in chip multiprocessors
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating sy...
Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishr...
ICDCS
2008
IEEE
16 years 15 days ago
Circumventing Server Bottlenecks: Indirect Large-Scale P2P Data Collection
In most large-scale peer-to-peer (P2P) applications, it is necessary to collect vital statistics data — sometimes referred to as logs — from up to millions of peers. Tradition...
Di Niu, Baochun Li
ICPP
2008
IEEE
16 years 14 days ago
Implementing and Exploiting Inevitability in Software Transactional Memory
—Transactional Memory (TM) takes responsibility for concurrent, atomic execution of labeled regions of code, freeing the programmer from the need to manage locks. Typical impleme...
Michael F. Spear, Michael Silverman, Luke Dalessan...
HPDC
2007
IEEE
16 years 11 days ago
Scalable, fault-tolerant management in a service oriented architecture
With the emergence of Service-based architectures, management of an application which comprises of a large number of distributed services becomes difficult as resources appear, mo...
Harshawardhan Gadgil, Geoffrey Fox, Shrideep Palli...