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ISCAS
2003
IEEE
77views Hardware» more  ISCAS 2003»
15 years 9 months ago
General iterative heuristics for VLSI multiobjective partitioning
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Aba...
IWSOC
2003
IEEE
96views Hardware» more  IWSOC 2003»
15 years 9 months ago
Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic
Boris D. Andreev, Edward L. Titlebaum, Eby G. Frie...
144
Voted
RSP
2003
IEEE
149views Control Systems» more  RSP 2003»
15 years 9 months ago
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA
In this paper, an efficient design flow integrating Mentor Graphics Precesion C and HDL designer is derived. In this hybrid prototyping environment, efficient FPGA architectures a...
Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cav...
ISLPED
2003
ACM
111views Hardware» more  ISLPED 2003»
15 years 9 months ago
A low-power VLSI architecture for turbo decoding
Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block...
Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer
90
Voted
APCCAS
2002
IEEE
151views Hardware» more  APCCAS 2002»
15 years 8 months ago
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform
Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen