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ICCAD
2003
IEEE
198views Hardware» more  ICCAD 2003»
15 years 6 months ago
A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits
This paper introduces a CAD framework for co-simulation of hybrid circuits containing CMOS and SET (Single Electron Transistor) devices. An improved analytical model for SET is al...
Santanu Mahapatra, Kaustav Banerjee, Florent Pegeo...
AICT
2006
IEEE
135views Communications» more  AICT 2006»
15 years 1 months ago
Improving Web Performance through New Networking Technologies
New connection-oriented networking technologies can provide quality-of-service guaranteed network connectivity required by some web-based applications. In this paper, we present a...
Xiuduan Fang, Xuan Zheng, Malathi Veeraraghavan
CORR
2010
Springer
158views Education» more  CORR 2010»
14 years 4 months ago
Efficient Approaches for Designing Fault Tolerant Reversible Carry Look-Ahead and Carry-Skip Adders
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
CCECE
2009
IEEE
15 years 2 months ago
A full-rate truly monolithic CMOS CDR for low-cost applications
A truly monolithic clock and data recovery (CDR) circuit for low cost low-end data communication systems has been realized in 0.6ȝm CMOS. The implemented CDR comprises a phase-an...
Bangli Liang, Zhigong Wang, Dianyong Chen, Bo Wang...
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
15 years 4 months ago
A comparison of via-programmable gate array logic cell circuits
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H...