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» Verifying VLSI Circuits
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DFT
2007
IEEE
100views VLSI» more  DFT 2007»
15 years 4 months ago
Soft Error Hardening for Asynchronous Circuits
Weidong Kuang, Casto Manuel Ibarra, Peiyi Zhao
DFT
2005
IEEE
92views VLSI» more  DFT 2005»
15 years 3 months ago
On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits
Jia Di, Parag K. Lala, D. P. Vasudevan
ISVLSI
2003
IEEE
99views VLSI» more  ISVLSI 2003»
15 years 2 months ago
Fast and Precise Power Prediction for Combinational Circuits
Hongping Li, John K. Antonio, Sudarshan K. Dhall
IJCNN
2007
IEEE
15 years 3 months ago
Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit
—The paper presents a silicon neuron circuit that mimics the behaviour of known classes of biological neurons. The circuit has been designed in a 0.35µm CMOS technology. The fir...
Jayawan H. B. Wijekoon, Piotr Dudek
VLSID
1995
IEEE
97views VLSI» more  VLSID 1995»
15 years 1 months ago
Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability
In this paper, we present methods for synthesizing multi-level asynchronous circuits to be both hazard-free
Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng