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» Work Stealing Technique and Scheduling on the Critical Path
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ISCA
2002
IEEE
96views Hardware» more  ISCA 2002»
15 years 2 months ago
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines
Leakage power is dominated by critical paths, and hence dynamic deactivation of fast transistors can yield large savings. We introduce metrics for comparing fine-grain dynamic de...
Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste...
INFOCOM
2006
IEEE
15 years 3 months ago
Policy-Based Resource Management and Service Provisioning in GMPLS Networks
— Emerging network applications tend to be built over heterogeneous network resources spanning multiple management domains. Many such applications have dynamic demands for dedica...
Xi Yang, Tom Lehman, Chris Tracy, Jerry Sobieski, ...
GRID
2004
Springer
15 years 3 months ago
Design and Analysis of a Dynamic Scheduling Strategy with Resource Estimation for Large-Scale Grid Systems
In this paper, we present a resource conscious dynamic scheduling strategy for handling large volume computationally intensive loads in a Grid system involving multiple sources an...
Sivakumar Viswanathan, Bharadwaj Veeravalli, Danto...
CASES
2006
ACM
15 years 3 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
HPCA
2012
IEEE
13 years 5 months ago
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads
Main memory latencies have always been a concern for system performance. Given that reads are on the critical path for CPU progress, reads must be prioritized over writes. However...
Niladrish Chatterjee, Naveen Muralimanohar, Rajeev...