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7

VLSID
1999
IEEE

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Multi-Valued Logic Synthesis

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Multi-Valued Logic Synthesis

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We survey some of the methods used for manipulating, representing, and optimizing multi-valued logic with the view of both building a better understanding of the more specialized binary-valued logic, as well as motivating research towards a true multi-valued multi-level optimization package.

Robert K. Brayton, Sunil P. Khatri

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Multi-valued Logic | Multi-valued Multi-level Optimization | Specialized Binary-valued Logic | VLSI | VLSID 1999 |

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Added	04 Aug 2010
Updated	04 Aug 2010
Type	Conference
Year	1999
Where	VLSID
Authors	Robert K. Brayton, Sunil P. Khatri

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