Embedded floating-point units in FPGAs

Due to their generic and highly programmable nature, FPGAs provide the ability to implement a wide range of applications. However, it is this nonspecific nature that has limited the use of FPGAs in scientific applications that require floating-point arithmetic. Even simple floating-point operations consume a large amount of computational resources. In this paper, we introduce embedding floating-point multiply-add units in an island style FPGA. This has shown to have an average area savings of 55.0% and an average increase of 40.7% in clock rate over existing architectures. Categories and Subject Descriptors C.4 [Performance of Systems]: Design Studies

• Type: Conference
• Year: 2006
• Where: FPGA
• Authors: Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert
• Keywords: Floating-point, Floating-point Multiply-add Units, FPGA, FPGA 2006, Simple Floating-point Operations