A gate resizing technique for high reduction in power consumption

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With the advent of portable and high density microelectronic devices, the power dissipation of VLSI circuits is becoming a critical concern. In this paper, we propose a post

Patrick Girard, Christian Landrault, Serge Pravoss

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1997
Where	ISLPED
Authors	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac

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A gate resizing technique for high reduction in power consumption

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