Adapting Application Mapping to Systematic Within-Die Process Variations on Chip Multiprocessors

Process variations, which lead to timing and power variations across identically-designed components, have been identified as one of the key future design challenges by the semiconductor industry. Using worst case latency/power assumptions is one option to address process variations. This option, while simplifying the problem, is becoming less and less attractive as its performance and power costs keep increasing. As a result, exploring options that allow the software to have knowledge about the actual latency/power consumption values is critical for future systems. Targeting systematic process variations, this paper makes two contributions. First, we discuss how we can assign threads to the cores of a chip multiprocessor (CMP) with process variations in mind and show the energy-delay product (EDP) benefits such a process variation-aware thread mapping can bring. Second, we study the benefits of varying the frequencies on a subset of the cores to increase EDP savings. We propose and...

• Type: Conference
• Year: 2009
• Where: HIPEAC
• Authors: Yang Ding, Mahmut T. Kandemir, Mary Jane Irwin, Padma Raghavan
• Keywords: EDP Savings, HIPEAC 2009, Process Variation, System Software, Systematic Process Variations