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ISVLSI
2007
IEEE

DSPstone Benchmark of CoDeL's Automated Clock Gating Platform

10 years 6 months ago
DSPstone Benchmark of CoDeL's Automated Clock Gating Platform
— We present a performance analysis of CoDeL, a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. It automatically inserts clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. In this paper we use the DSPstone benchmark to thoroughly evaluate the CoDeL platform for the design of power efficient DSP architectures. We find that, compared to DSPs, the CoDeL platform produces designs with comparable clock cycle counts but faster run times, and dramatically lower power dissipation. Next we use power analysis to compare the effectiveness of CoDeL’s automated clock gating as compared to automated clock gating using Synopsys tools. A simulation based power analysis shows that CoDeL’s clock gating performs better than Synopsys’ automated clock gating. CoDeL reduces the power dissipation by 72% on average, while Synopsys gives 63% savings.
Nainesh Agarwal, Nikitas J. Dimopoulos
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISVLSI
Authors Nainesh Agarwal, Nikitas J. Dimopoulos
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