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ICCAD
1999
IEEE

Implication graph based domino logic synthesis

9 years 10 months ago
Implication graph based domino logic synthesis
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid significant area penalty resulting from duplication. To maximize the domino logic part and to minimize the static CMOS logic part, a generalized ATPG based logic transformation is proposed to eliminate or relocate a target inverter. Based on the new concept of dominating set of mandatory assignment (DSMA) and the corresponding implication graph, we propose algorithms to identify a minimum candidate set for a target inverter. Experimental results show that logic transformation based on implication graph can reduce transistor counts by 25% and power delay product by 25% on average.
Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ICCAD
Authors Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
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