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ICCAD
1998
IEEE
90views Hardware» more  ICCAD 1998»
9 years 8 months ago
Technology mapping for domino logic
Domino logic is a popular con guration for implementing high-speed circuits. An algorithm for domino logic mapping, under a parameterized library style, is presented here. Practic...
Min Zhao, Sachin S. Sapatnekar
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
9 years 8 months ago
Timing-driven partitioning for two-phase domino and mixed static/domino implementations
Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timi...
Min Zhao, Sachin S. Sapatnekar
ICCAD
1999
IEEE
96views Hardware» more  ICCAD 1999»
9 years 8 months ago
Implication graph based domino logic synthesis
In this paper, we present a new approach to the problem of inverter elimination in domino logic synthesis. A small piece of static CMOS logic is introduced to the circuit to avoid...
Ki-Wook Kim, C. L. Liu, Sung-Mo Kang
ICCD
2000
IEEE
137views Hardware» more  ICCD 2000»
9 years 8 months ago
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
In this paper; we present a noise-immune highperformance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Do...
Alexandre Solomatnikov, Kaushik Roy, Cheng-Kok Koh...
DFT
2000
IEEE
105views VLSI» more  DFT 2000»
9 years 8 months ago
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang...
ATS
2000
IEEE
149views Hardware» more  ATS 2000»
9 years 8 months ago
Charge sharing fault analysis and testing for CMOS domino logic circuits
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor design. However, domino logic ...
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Sh...
GLVLSI
2002
IEEE
135views VLSI» more  GLVLSI 2002»
9 years 8 months ago
Low swing dual threshold voltage domino logic
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
Volkan Kursun, Eby G. Friedman
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
9 years 9 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
9 years 9 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
DAC
2004
ACM
10 years 4 months ago
Post-layout logic optimization of domino circuits
Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, w...
Aiqun Cao, Cheng-Kok Koh
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