31 search results - page 1 / 7 » Quality considerations in delay fault testing |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
ISQED
2003
IEEE
13 years 9 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
VTS
2007
IEEE
13 years 10 months ago
2007
IEEE
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
ET
2002
13 years 4 months ago
2002
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...