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» Quality considerations in delay fault testing
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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
9 years 2 months ago
Quality considerations in delay fault testing
We examine delay models used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which signi cantly a ect the actual...
Alicja Pierzynska, Slawomir Pilarski
ISQED
2003
IEEE
147views Hardware» more  ISQED 2003»
9 years 4 months ago
On Structural vs. Functional Testing for Delay Faults
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li...
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
9 years 5 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
9 years 5 months ago
A dynamic test compaction procedure for high-quality path delay testing
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, T...
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