5 search results - page 1 / 1 » A BIST Scheme for an SNR Test of a Sigma-Delta ADC |
ITC
1993
IEEE
13 years 9 months ago
1993
IEEE
Built-In-Self-Test BIST for VLSI systems is desirable in order to reduce the cost per chip of production-time testing by the manufacturer. In addition, it can provide the means ...
ISCAS
2011
IEEE
12 years 9 months ago
2011
IEEE
—Linearity and spectral performance test contributes most cost of ADC test. This paper presents a new method for testing an ADC’s SNR from its linearity test data. The method d...
DATE
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper, we present a BIST scheme for testing onchip AD and DA converters. We discuss on-chip generation of linear ramps as test stimuli, and propose techniques for measurin...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper presents a scheme for testing DACs’ static non-linearity errors by using a two-step flash ADC with deterministic dynamic element matching (DDEM). In this work, the...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...