16 search results - page 3 / 4 » A Novel Low-Power Scan Design Technique Using Supply Gating |
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
ICCAD
2001
IEEE
14 years 2 months ago
2001
IEEE
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...
TIM
2010
13 years 15 days ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...