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DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 8 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
VTS
2003
IEEE
81views Hardware» more  VTS 2003»
13 years 10 months ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
13 years 11 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
13 years 11 months ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...