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» A datapath synthesis system for the reconfigurable datapath ...
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DATE
2010
IEEE
140views Hardware» more  DATE 2010»
13 years 9 months ago
Construction of dual mode components for reconfiguration aware high-level synthesis
High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area...
George Economakos, Sotirios Xydis, Ioannis Koutras...
ISCAS
2005
IEEE
125views Hardware» more  ISCAS 2005»
13 years 11 months ago
A methodology for partitioning DSP applications in hybrid reconfigurable systems
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
Michalis D. Galanis, Athanasios Milidonis, George ...
DFT
2005
IEEE
83views VLSI» more  DFT 2005»
13 years 11 months ago
An ILP Formulation for Yield-driven Architectural Synthesis
Data flow graph dominant designs, such as communication video and audio applications, are common in today’s IC industry. In these designs, the datapath resources (e.g., adders,...
Zhaojun Wo, Israel Koren, Maciej J. Ciesielski
DAC
2010
ACM
13 years 5 months ago
Automatic multithreaded pipeline synthesis from transactional datapath specifications
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timo...
DATE
2009
IEEE
171views Hardware» more  DATE 2009»
14 years 1 days ago
Automatic generation of streaming datapaths for arbitrary fixed permutations
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...
Peter A. Milder, James C. Hoe, Markus Püschel