102 search results - page 2 / 21 » A design platform for 90-nm leakage reduction techniques |
DAC
2005
ACM
13 years 7 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract— We study leakage-power reduction in standby random access memories (SRAMs) during data-retention. An SRAM cell requires a minimum critical supply voltage (DRV) above wh...
TCAD
2008
13 years 5 months ago
2008
As CMOS technology is scaled down toward the nanoscale regime, drastically growing leakage currents and variations in device characteristics are becoming two important design chall...
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
We present an error-tolerant SRAM design optimized for ultra-low standby power. Using SRAM cell optimization techniques, the maximum data retention voltage (DRV) of a 90nm 26kb SR...