27 search results - page 1 / 6 » A distributed FIFO scheme for on chip communication |
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
CSREAESA
2004
13 years 6 months ago
2004
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
ICCD
1996
IEEE
13 years 8 months ago
1996
IEEE
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In thi...
IPPS
2006
IEEE
13 years 10 months ago
2006
IEEE
This paper deals with scheduling divisible load applications on star networks, in presence of return messages. This work is a follow-on of [6, 7], where the same problem was consi...