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» A distributed FIFO scheme for on chip communication
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ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
10 years 5 months ago
A distributed FIFO scheme for on chip communication
— Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because of disturbances that result from parasiti...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
CSREAESA
2004
10 years 29 days ago
A Distributed FIFO Scheme for System on Chip Inter-Component Communication
Interconnect delays are increasingly becoming the dominant source of performance degradation in the nano-meter regime, largely because the wires do not scale as fast as the device...
Ray Robert Rydberg III, Jabulani Nyathi, Jos&eacut...
ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
10 years 5 months ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
ICCD
1996
IEEE
134views Hardware» more  ICCD 1996»
10 years 3 months ago
Pausible Clocking: A First Step Toward Heterogeneous Systems
This paper describes a novel communication scheme, which is guaranteed to be free of synchronization failures, amongst multiple synchronous modules operating independently. In thi...
Kenneth Y. Yun, Ryan P. Donohue
IPPS
2006
IEEE
10 years 5 months ago
FIFO scheduling of divisible loads with return messages under the one-port model
This paper deals with scheduling divisible load applications on star networks, in presence of return messages. This work is a follow-on of [6, 7], where the same problem was consi...
Olivier Beaumont, Loris Marchal, Veronika Rehn, Yv...
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