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GLVLSI
2005
IEEE
152views VLSI» more  GLVLSI 2005»
13 years 10 months ago
A high speed and leakage-tolerant domino logic for high fan-in gates
Robustness of high fan-in domino circuits is degraded by technology scaling due to exponential increase in leakage. In this paper, we propose a new domino circuit for high fan-in ...
Farshad Moradi, Hamid Mahmoodi-Meimand, Ali Peirav...
PATMOS
2004
Springer
13 years 10 months ago
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana
ASPDAC
2005
ACM
115views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Low-power domino circuits using NMOS pull-up on off-critical paths
- Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power. We propose ...
Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhij...
ICCAD
2003
IEEE
135views Hardware» more  ICCAD 2003»
13 years 9 months ago
ATPG for Noise-Induced Switch Failures in Domino Logic
Domino circuits have been used in most modern high-performance microprocessor designs because of their high speed, low transistor-count and hazard-free operation. However, with te...
Rahul Kundu, R. D. (Shawn) Blanton
GLVLSI
2003
IEEE
195views VLSI» more  GLVLSI 2003»
13 years 9 months ago
A pipelined clock-delayed domino carry-lookahead adder
Clock-delayed (CD) domino is a dynamic logic family developed to provide both inverting and non-inverting logic on single-rail gates. It is self-timed and can be easily pipelined ...
Bhushan A. Shinkre, James E. Stine