54 search results - page 2 / 11 » A new state assignment technique for testing and low power |
DAC
1997
ACM
13 years 8 months ago
1997
ACM
An ATPG technique is proposed that reduces heat dissipation during testing of sequential circuits that have full-scan. The objective is to permit safe and inexpensive testing of l...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
A new circuit technique is proposed in this paper for simultaneously reducing the subthreshold and gate oxide leakage power in domino logic circuits. PMOS-only sleep transistors ar...
ICCD
2002
IEEE
14 years 1 months ago
2002
IEEE
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
ASPDAC
2000
ACM
13 years 9 months ago
2000
ACM
Abstract— Clock-gating techniques are very effective in the reduction of the switching activity in sequential logic circuits. In particular, recent work has shown that significa...
IOLTS
2008
IEEE
13 years 11 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...