179 search results - page 1 / 36 » A new test pattern generation method for delay fault testing |
VTS
1996
IEEE
13 years 9 months ago
1996
IEEE
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
- We propose a dynamic test compaction procedure to generate high-quality test patterns for path delay faults. While the proposed procedure generates a compact two-pattern test set...
DATE
1997
IEEE
13 years 9 months ago
1997
IEEE
Many Built-In Self Test pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs o...
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...