24 search results - page 1 / 5 » A selective pattern-compression scheme for power and test-da... |
ICCAD
2007
IEEE
14 years 1 months ago
2007
IEEE
— This paper proposes a selective pattern-compression scheme to minimize both test power and test data volume during scan-based testing. The proposed scheme will selectively supp...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Significant reductions in test application times can be achieved through parallelizing core tests; however, simultaneous test of various cores may result in exceeding power thres...
ICCAD
2008
IEEE
14 years 1 months ago
2008
IEEE
Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ...
DATE
2009
IEEE
13 years 8 months ago
2009
IEEE
Growing test data volume and overtesting caused by excessive scan capture power are two of the major concerns for the industry when testing large integrated circuits. Various test...
ISQED
2010
IEEE
13 years 10 months ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...