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ASPDAC
2007
ACM
140views Hardware» more  ASPDAC 2007»
10 years 6 months ago
An Architecture for Combined Test Data Compression and Abort-on-Fail Test
1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
Erik Larsson, Jon Persson
ASPDAC
2008
ACM
115views Hardware» more  ASPDAC 2008»
10 years 4 months ago
GECOM: Test data compression combined with all unknown response masking
This paper introduces GECOM technology, a novel test compression method with seamless integration of test GE
Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsu...
ET
2002
111views more  ET 2002»
10 years 2 months ago
Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
Huaguo Liang, Sybille Hellebrand, Hans-Joachim Wun...
ICCD
2003
IEEE
130views Hardware» more  ICCD 2003»
10 years 11 months ago
On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
10 years 8 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
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