1 The low throughput at IC (Integrated Circuit) testing is mainly due to the increasing test data volume, which leads to high ATE (Automatic Test Equipment) memory requirements and...
In this paper a novel architecture for scan-based mixed mode BIST is presented. To reduce the storage requirements for the deterministic patterns it relies on a two-dimensional co...
This paper presents a pinpoint test set relaxation method for test compression that maximally derives the capability of a run-length encoding technique such as Golomb coding or fr...
Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Cha...
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...