114 search results - page 2 / 23 » Architecture and synthesis for multi-cycle communication |
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
ISPD
2003
ACM
13 years 10 months ago
2003
ACM
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
In deep submicron technology, wire delay is no longer negligible and is gradually dominating the system latency. Some state-of-the-art architectural synthesis flows adopt the distr...
DATE
2009
IEEE
14 years 2 days ago
2009
IEEE
In this paper, a novel design space exploration approach is proposed that enables a concurrent optimization of the topology, the process binding, and the communication routing of ...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
