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RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
13 years 10 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
DAC
2012
ACM
11 years 7 months ago
Chisel: constructing hardware in a Scala embedded language
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
Jonathan Bachrach, Huy Vo, Brian Richards, Yunsup ...
FPL
2006
Springer
223views Hardware» more  FPL 2006»
13 years 8 months ago
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation
This paper presents a novel tool flow combining rewriting logic with hardware synthesis. It enables the automated generation of synthesizable VHDL code from mathematical equations...
Carlos Morra, M. Sackmann, Sunil Shukla, Jürg...
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
13 years 12 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
DATE
2008
IEEE
199views Hardware» more  DATE 2008»
13 years 11 months ago
Safe Automatic Flight Back and Landing of Aircraft Flight Reconfiguration Function (FRF)
SOFIA (Safe Automatic Flight Back and Landing of Aircraft) project is a response to the challenge of developing concepts and techniques enabling the safe and automatic return to g...
Juan Alberto Herreria Garcia