Sciweavers

58 search results - page 1 / 12
» Characterizing Linear Size Circuits in Terms of Privacy
Sort
View
STOC
1996
ACM
118views Algorithms» more  STOC 1996»
13 years 9 months ago
Characterizing Linear Size Circuits in Terms of Privacy
In this paper we prove a perhaps unexpected relationship between the complexity class of the boolean functions that have linear size circuits, and n-party private protocols. Speci...
Eyal Kushilevitz, Rafail Ostrovsky, Adi Rosé...
DATE
2004
IEEE
157views Hardware» more  DATE 2004»
13 years 8 months ago
Hierarchical Modeling and Simulation of Large Analog Circuits
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog circuits. The new algorithm can perform circuit complexity reduction...
Sheldon X.-D. Tan, Zhenyu Qi, Hang Li
DAC
2005
ACM
13 years 6 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
GLVLSI
2003
IEEE
219views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Buffer sizing for minimum energy-delay product by using an approximating polynomial
This paper first presents an accurate and efficient method of estimating the short circuit energy dissipation and the output transition time of CMOS buffers. Next the paper descri...
Chang Woo Kang, Soroush Abbaspour, Massoud Pedram
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
13 years 10 months ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan