14 search results - page 3 / 3 » Classbased Detailed Routing in VLSI Design |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
In many applications such as high-level synthesis (HLS) and logic synthesis and possibly engineering change order (ECO) we would like to get fast and accurate estimations of diffe...
ASYNC
2003
IEEE
13 years 10 months ago
2003
IEEE
The lack of proven mechanisms for transferring data between multiple synchronous islands has been a major impediment for applying globally asynchronous locally synchronous (GALS) ...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
SLIP
2005
ACM
13 years 10 months ago
2005
ACM
Routability optimization has become a major concern in the physical design cycle of VLSI circuits. Due to the recent advances in VLSI technology, interconnect has become a dominan...