23 search results - page 1 / 5 » Device and technology optimizations for low power design in ... |
VLSID
2006
IEEE
13 years 10 months ago
2006
IEEE
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
ISLPED
1997
ACM
13 years 9 months ago
1997
ACM
GLVLSI
2003
IEEE
13 years 10 months ago
2003
IEEE
One of the fundamental problems in Deep Sub Micron (DSM) circuits is Simultaneous Switching Noise (SSN), which causes voltage fluctuations in the circuit power/ground networks. In...
ISQED
2006
IEEE
13 years 10 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
ISLPED
1997
ACM
13 years 8 months ago
1997
ACM
In this paper we report the fully depleted CMOS/SOI device design guidelines for low power applications. Optimal technology, device and circuit parameters are discussed and compar...