38 search results - page 1 / 8 » Electrothermal analysis and optimization techniques for nano... |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Abstract— With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of ele...
TIM
2010
12 years 11 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ICCAD
2009
IEEE
13 years 2 months ago
2009
IEEE
In this paper, we propose a new technique, referred to as virtual probe (VP), to efficiently measure, characterize and monitor both inter-die and spatially-correlated intra-die va...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Negative bias temperature instability (NBTI) has become the dominant reliability concern for nanoscale PMOS transistors. In this paper, a predictive model is developed for the deg...
TVLSI
2008
13 years 4 months ago
2008
As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...