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» Exploration of Low Power Adders for a SIMD Data Path
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ASPDAC
2007
ACM
185views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Exploration of Low Power Adders for a SIMD Data Path
Giacomo Paci, Paul Marchal, Luca Benini
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
13 years 6 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
FPL
2005
Springer
125views Hardware» more  FPL 2005»
13 years 10 months ago
Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor
This paper describes novel data-path architecture for FPGA-based multimedia processors. The proposed circuit can adapt itself at run-time to different operations and data wordleng...
Marco Lanuzza, Stefania Perri, Martin Margala, Pas...
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha