22 search results - page 1 / 5 » FPGA Interconnect Delay Fault Testing |
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
ET
2006
13 years 4 months ago
2006
We present an efficient built-in self-test (BIST) architecture for testing and diagnosing stuck-at faults, delay faults, and bridging faults in FPGA interconnect resources. The BIS...
ITC
2002
IEEE
13 years 9 months ago
2002
IEEE
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
IOLTS
2000
IEEE
13 years 9 months ago
2000
IEEE
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. Th...
TCAD
2002
13 years 4 months ago
2002
As IC densities are increasing, cluster-based FPGA architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-based architecture is one in which...