Sciweavers

21 search results - page 3 / 5
» Fault Diagnosis in Scan-Based BIST
Sort
View
ISQED
2003
IEEE
83views Hardware» more  ISQED 2003»
13 years 11 months ago
Compact Dictionaries for Fault Diagnosis in BIST
We present a new technique for generating compact dictionaries for cause-effect diagnosis in BIST. This approach relies on the use of three compact dictionaries: (i) D1, containin...
Chunsheng Liu, Krishnendu Chakrabarty
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 12 days ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...
ITC
1999
IEEE
73views Hardware» more  ITC 1999»
13 years 10 months ago
Fault diagnosis in scan-based BIST using both time and space information
Jayabrata Ghosh-Dastidar, Debaleena Das, Nur A. To...
ITC
2003
IEEE
149views Hardware» more  ITC 2003»
13 years 11 months ago
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
Ramesh C. Tekumalla
CSREAESA
2009
13 years 7 months ago
Embedded Processor Based Fault Injection and SEU Emulation for FPGAs
Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip...
Bradley F. Dutton, Mustafa Ali, Charles E. Stroud,...