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» Gate sizing for large cell-based designs
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FCCM
2006
IEEE
125views VLSI» more  FCCM 2006»
13 years 11 months ago
A Multithreaded Soft Processor for SoPC Area Reduction
The growth in size and performance of Field Programmable Gate Arrays (FPGAs) has compelled System-on-aProgrammable-Chip (SoPC) designers to use soft processors for controlling sys...
Blair Fort, Davor Capalija, Zvonko G. Vranesic, St...
ITC
2003
IEEE
151views Hardware» more  ITC 2003»
13 years 11 months ago
Fault Collapsing via Functional Dominance
A fault fj is said to dominate another fault fi if all tests for fi detect fj . When two faults dominate each other, they are called equivalent. Dominance and equivalence relation...
Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusuda...
ERSA
2006
113views Hardware» more  ERSA 2006»
13 years 7 months ago
A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead
Thermal monitoring of a design plays a vital role to ensure safe and reliable thermal operating conditions. Thermal monitoring by employing thermal sensors is a popular technique ...
Rajarshi Mukherjee, Somsubhra Mondal, Seda Ogrenci...
DAC
2009
ACM
13 years 10 months ago
Vicis: a reliable network for unreliable silicon
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacc...
GLVLSI
1998
IEEE
124views VLSI» more  GLVLSI 1998»
13 years 9 months ago
Non-Refreshing Analog Neural Storage Tailored for On-Chip Learning
In this research, we devised a new simple technique for statically holding analog weights, which does not require periodic refreshing. It further contains a mechanism to locally u...
Bassem A. Alhalabi, Qutaibah M. Malluhi, Rafic A. ...