52 search results - page 1 / 11 » Low Power BIST Based on Scan Partitioning |
DFT
2005
IEEE
13 years 6 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
ITC
2000
IEEE
13 years 9 months ago
2000
IEEE
A deterministic partitioning technique for fault diagnosis in Scan-Based BIST is proposed. Properties of high quality partitions for improved fault diagnosis times are identified...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
ITC
2003
IEEE
13 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
ATS
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...