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» Low-Power Soft Error Hardened Latch
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JOLPE
2010
97views more  JOLPE 2010»
13 years 3 months ago
Low-Power Soft Error Hardened Latch
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...
Hossein Karimiyan Alidash, Vojin G. Oklobdzija
IOLTS
2008
IEEE
102views Hardware» more  IOLTS 2008»
13 years 11 months ago
Integrating Scan Design and Soft Error Correction in Low-Power Applications
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
Michael E. Imhof, Hans-Joachim Wunderlich, Christi...
DFT
2005
IEEE
72views VLSI» more  DFT 2005»
13 years 10 months ago
Soft Error Modeling and Protection for Sequential Elements
Sequential elements, flip-flops, latches, and memory cells, are the most vulnerable components to soft errors. Since state-of-the-art designs contain millions of bistables, it i...
Hossein Asadi, Mehdi Baradaran Tahoori
DATE
2009
IEEE
202views Hardware» more  DATE 2009»
13 years 11 months ago
Design as you see FIT: System-level soft error analysis of sequential circuits
Soft errors in combinational and sequential elements of digital circuits are an increasing concern as a result of technology scaling. Several techniques for gate and latch hardeni...
Daniel Holcomb, Wenchao Li, Sanjit A. Seshia