41 search results - page 4 / 9 » Mapping DSP applications on processor systems with coarse-gr... |
MJ
2006
13 years 5 months ago
2006
In this paper, we propose a method for speeding-up Digital Signal Processing applications by partitioning them between the reconfigurable hardware blocks of different granularity ...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
TVLSI
2008
2008
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
13 years 5 months ago
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
SASP
2009
IEEE
14 years 1 days ago
2009
IEEE
— As growing power dissipation and thermal effects disrupted the rising clock frequency trend and threatened to annul Moore’s law, the computing industry has switched its route...
DATE
2009
IEEE
14 years 1 days ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...